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Failure Mechanism and Failure Phenomenon of Protection Components under EOS

The failure of semiconductor components at the application end is mainly caused by various kinds of overstress. The overstress appears most commonly with slow or sudden change of the working environment. When the working environment of the semiconductor components changes and generates stress beyond the maximum tolerable stress of the device, the component fails. There are many different types of stresses (as shown in Table 1), among which failure due to electrical overstress (EOS) is more common than others.


 

Table 1: Stress type, testing method and failure modes


EOS failure can be divided into chip-level EOS and system-level EOS.

During transportation, assembly and testing, ESD energy enters the IC chip through port metal pins or through air coupling, damaging the ESD protection unit at the port or internal logic circuit. Consequently, it causes local short circuit, open circuit or latch-up, resulting the failure in the IC logic function.

In the whole system, although the designer has carried out subtly wiring, and added a large number of transient suppression diodes (TVS) to improve the system-level resistance to EOS. However, due to the complex working environment of the whole system, there is still a certain probability of failure. The damage to TVS at the port and the chip inside the port are most common.

This article analyzes the phenomena and mechanisms of semiconductor component failure in various extreme electrical stress environments. By simulating different EOS (static electricity, surge, DC overvoltage), this article also analyzes how to reduce the harm of EOS by using TVS.

Simulation of electrostatic failure phenomenon
The product WE05MUC is widely used in the electrostatic and low voltage surge protection of high-speed data ports. It has the electrostatic protection capability of IEC 61000-4-2 (ESD) ±25kV (CONTACT). When it is impacted by electrostatic energy beyond its capability of IEC 61000-4-2 (ESD) ±30kV (contact), it will fail.

Figure 1 and Figure 2 show the local chip failure caused by simulated static electricity. It can be seen that the failure phenomenon is slightly different among the samples. However, several conductive pathways are all burned out, indicating that the structure design is reasonable and the ESD energy is evenly distributed.


 

Figure 1: Local chip failure caused by simulated static electricity A


 

Figure 2: Local chip failure caused by simulated static electricity B



Main characteristics of electrostatic failure:


1.Electrostatic damages can be divided into two types: damage failure and potential failure. Damage failure means that the component is damaged after an ESD event and loses partially or completely its function. Compare to damage failure, the electrostatic energy is at a critical level by potential failure. After the electrostatic discharge, it causes only minor damage and slight changes in the electrical parameters of the component, yet still qualified;

2.The appearance of electrostatic damage varies greatly from component to component. Sometimes obvious burn marks can be seen, and sometimes only minor damage marks are visible with a high-powered microscope. In some possible cases, the metal layer may need to be removed before the damage point can be observed.

Electrostatic damage in the entire circuit can be divided into two failure modes:

1.Protection component TVS damaged: Take other parameters into consideration and choose component with a higher protection level;

2.Back-end circuit damaged: Mainly related to the high TVS electrostatic clamping voltage, it is necessary to take other parameters into consideration and choose a TVS component with a lower electrostatic clamping voltage.

Simulation of surge failure phenomenon


The product WS1029HP in DFN1610 package is suitable for high voltage fast charging Vbat port with the operating voltage of 10V. It has surge IEC 61000-4-5 (Lightning) 8/20μs IPP 160A through-current capability, and will fail when it is subjected to a surge beyond its capability of 170A and above.

Figure 3 and Figure 4 show the local chip failure caused by simulated surge.


 

Figure 3: Local chip failure caused by simulated surge A


 

Figure 4: Local chip failure caused by simulated surge B



Main characteristics of surge failure:


1.The failure point is most likely to occur at the PN junction position at the edge of the device or near the solder line, because the PN junction, especially the corner position is generally the weakest position of the entire component;

2.Chip damage area is relatively small and the burn point can be directly observed;

3.Normally the solder wire will not melt. However, there is still a certain chance that the solder wire will be damaged and melted if the surge energy is too large.

Surge damage in the entire circuit is divided into two failure modes:


1.Protection component TVS damaged: Take other parameters into consideration and choose component with a higher flow-through capacity;

2.Back-end circuit damaged: Mainly related to the high TVS electrostatic clamping voltage, it is necessary to take other parameters into consideration and choose a TVS component with a lower clamping voltage.

Simulation of DC overvoltage failure phenomenon


The product WS1029QP in DFN1610 package is suitable for high voltage fast charging Vbus port with the operating voltage of 15V. It has surge IEC 61000-4-5 (Lightning) 8/20μs IPP 120A flow-through capability. Its breakdown voltage is 17V, and the component fails when a 20V DC voltage is applied directly without any current limiting at the same time.

Figure 5 and Figure 6 show the local chip failure caused by simulated DC overvoltage.


 

Figure 5: Local chip failure caused by simulated DC overvoltage A


 

Figure 6: Local chip failure caused by simulated DC overvoltage B



Main characteristics of DC overvoltage failure:

1.The failure point usually appears in the center area of the chip. 
Since DC overvoltage damage occurs with high energy and long duration, the extremely high energy has enough time to be transmitted to the center of the chip. As heat builds up and temperature rises, the chip is damaged and a melt channel is generated.

2.Chip damage area is relatively large. 
Usually it turns out to be extensive burns, or even carbonization of the front metal.

3.Solder wire often melts.
Solder wire is relatively thin, with large impedance and serious heat generation. Long time heat will melt the solder wire and even burn the plastic seal body.

DC overvoltage damage in the entire circuit is divided into two failure modes:

1.Occasional voltage fluctuations beyond the designer's expectations
As the fluctuations last for microseconds or milliseconds, they lead to TVS damage. First, the TVS fails with a short circuit, the system malfunctions and the potential of power supply is pulled down; without timely intervention, the TVS may transform into an open circuit and high voltage acts on the back-end circuit with the possibility of a damaged back-end circuit.

2.Improper component choice
The lower limit of breakdown voltage is lower than the upper limit of operating voltage fluctuation. Damage to TVS occurs with insufficient margin.

In conclusion, the designer should fully evaluate the various possibilities of electrical over stress in the design process of the entire circuit. First, designer should determine the goals of a EOS design and take into account the performance indexes of the components used and their capability to resist EOS. Then, suitable components could be selected and the related testing and evaluation should be completed to improve the reliability of the entire machine.

For more detailed product data, see protection component parameter table on our website under "Product Center". Using filter function by selecting the operating voltage range and number of channels to narrow down the available options.


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